Low Power Networks-on-Chip

Network on-Chip (NoC) is an interconnect fabric to connect sub-system blocks on a chip. The NoC should provide high bandwidth and low latency, should consume low energy, and should be compact. However, all these requirements are at odds and require tradeoffs at all levels. In this chapter, we discuss issues and challenges for future NoCs with demands for high bandwidth and low energy. Next, we present details of how coupling packet-switched arbitration with circuit-switched data transfer can achieve these goals. In this hybrid network, packet-switched arbitration is used to reserve future circuit-switched channels for the data transfer, eliminating the performance bottlenecks associated with pure circuit-switched networks while maintaining their power advantage. Furthermore, proximity-based data streaming increases network throughput and improves energy efficiency. Measurements of this NoC in 45 nm CMOS are described to analyze design tradeoffs. 1.1 Network on-Chip: Past, Present, and the Future Network on-Chip (NoC) has evolved from the good old supercomputer days where computers in a cabinet, as well as multiple cabinets, were connected together to form a complete parallel computer system. These networks were primitive indeed, such as simple Ethernet at times, nevertheless sufficient to provide the necessary bandwidth with acceptable latencies. That was then, and now, with technology scaling over several generations, you can afford to have several computers themselves on a single die, connected together by a network forming a homogeneous many-core parallel computer system. To take it even further, the integration capacity is now so vast that it is possible to integrate diverse functional blocks on a chip, to be connected by a communication network, to form a heterogeneous system, what we call a system on-chip or SoC. And the network that connects these functional blocks together is the backbone of such a system. In this chapter, we discuss the state of the art in this M.A. Anders ( ) Intel Corporation, Hillsboro, OR, USA e-mail: [email protected] C. Silvano et al. (eds.), Low Power Networks-on-Chip, DOI 10.1007/978-1-4419-6911-8 1, c Springer Science+Business Media, LLC 2011 3 4 M.A. Anders et al. field, the issues and challenges that we will face in the future, and some of the prominent work addressing these issues. We also propose a hybrid packet/circuit-switched network that combines network advantages, higher resource utilization of packetswitched networks, and low power consumption of circuit-switched networks, to improve the energy-efficiency. The energy-efficiency advantage and design tradeoffs will be quantified with silicon measurements of an 8 8 mesh NoC in 45 nm CMOS. 1.1.1 State of the Art in NoCs Evolution of the NoC occurred over the last 3 decades, from early days of single chip microcontrollers incorporating several simple functional blocks, to today’s sophisticated SoCs integrating diverse functional blocks on a chip. The early NoCs were good enough for the purpose, and as the bandwidth demand increased, they morphed into even sophisticated networks, with higher order topologies implemented with complex switches. Let us examine the evolution, comparing and contrasting their benefits as they evolved.